Reduction of thickness variations of a threshold semiconductor alloy by reducing patterning non-uniformities prior to depositing the semiconductor alloy

ABSTRACT

The growth rate in a selective epitaxial growth process for depositing a threshold adjusting semiconductor alloy, such as a silicon/germanium alloy, may be enhanced by performing a plasma-assisted etch process prior to performing the selective epitaxial growth process. For example, a mask layer may be patterned on the basis of the plasma-assisted etch process, thereby simultaneously providing superior device topography during the subsequent growth process. Hence, the threshold adjusting material may be deposited with enhanced thickness uniformity, thereby reducing overall threshold variability.

BACKGROUND OF THE INVENTION

1. Field of the Invention

Generally, the present disclosure relates to sophisticated integratedcircuits including advanced transistor elements that comprise highlycapacitive gate structures including a metal-containing electrode and ahigh-k gate dielectric of increased permittivity compared to gatedielectrics, such as silicon dioxide and silicon nitride.

2. Description of the Related Art

The fabrication of advanced integrated circuits, such as CPUs, storagedevices, ASICs (application specific integrated circuits) and the like,requires a large number of circuit elements to be formed on a given chiparea according to a specified circuit layout, wherein field effecttransistors represent one important type of circuit elements thatsubstantially determine performance of the integrated circuits.Generally, a plurality of process technologies are currently practiced,wherein, for many types of complex circuitry, including field effecttransistors, MOS technology is currently one of the most promisingapproaches due to the superior characteristics in view of operatingspeed and/or power consumption and/or cost efficiency. During thefabrication of complex integrated circuits using, for instance, MOStechnology, millions of transistors, e.g., N-channel transistors and/orP-channel transistors, are formed on a substrate including a crystallinesemiconductor layer. A field effect transistor, irrespective of whetheran N-channel transistor or a P-channel transistor is considered,typically comprises so-called PN junctions that are formed by aninterface of highly doped regions, referred to as drain and sourceregions, with a slightly doped or non-doped region, such as a channelregion, disposed adjacent to the highly doped regions. In a field effecttransistor, the conductivity of the channel region, i.e., the drivecurrent capability of the conductive channel, is controlled by a gateelectrode formed adjacent to the channel region and separated therefromby a thin insulating layer. The conductivity of the channel region, uponformation of a conductive channel due to the application of anappropriate control voltage to the gate electrode, depends on the dopantconcentration, the mobility of the charge carriers and, for a givenextension of the channel region in the transistor width direction, onthe distance between the source and drain regions, which is alsoreferred to as channel length. Hence, in combination with the capabilityof rapidly creating a conductive channel below the insulating layer uponapplication of the control voltage to the gate electrode, theconductivity of the channel region substantially affects the performanceof MOS transistors. Thus, as the speed of creating the channel, whichdepends on the conductivity of the gate electrode, and the channelresistivity substantially determine the transistor characteristics, thescaling of the channel length, and associated therewith the reduction ofchannel resistivity and reduction of gate resistivity, is a dominantdesign criterion for accomplishing an increase in the operating speed ofthe integrated circuits.

Presently, the vast majority of integrated circuits is fabricated on thebasis of silicon due to the substantially unlimited availabilitythereof, the well-understood characteristics of silicon and relatedmaterials and processes and the experience gathered over the last 50years. Therefore, silicon will likely remain the material of choice inthe foreseeable future for circuit generations designed for massproducts. One reason for the importance of silicon in fabricatingsemiconductor devices has been the superior characteristics of asilicon/silicon dioxide interface that allows reliable electricalinsulation of different regions from each other. The silicon/silicondioxide interface is stable at high temperatures and, thus, allows theperformance of subsequent high temperature processes, as are required,for example, for anneal cycles to activate dopants and to cure crystaldamage without sacrificing the electrical characteristics of theinterface.

For the reasons pointed out above, in field effect transistors, silicondioxide is preferably used as a gate insulation layer that separates thegate electrode, frequently comprised of polysilicon or othermetal-containing materials, from the silicon channel region. In steadilyimproving device performance of field effect transistors, the length ofthe channel region has continuously been decreased to improve switchingspeed and drive current capability. Since the transistor performance iscontrolled by the voltage supplied to the gate electrode to invert thesurface of the channel region to a sufficiently high charge density forproviding the desired drive current for a given supply voltage, acertain degree of capacitive coupling, provided by the capacitor formedby the gate electrode, the channel region and the silicon dioxidedisposed therebetween, has to be maintained. It turns out thatdecreasing the channel length requires an increased capacitive couplingto avoid the so-called short channel behavior during transistoroperation. The short channel behavior may lead to an increased leakagecurrent and to a pronounced dependence of the threshold voltage on thechannel length. Aggressively scaled transistor devices with a relativelylow supply voltage and thus reduced threshold voltage may suffer from anexponential increase of the leakage current while also requiringenhanced capacitive coupling of the gate electrode to the channelregion. Thus, the thickness of the silicon dioxide layer has to becorrespondingly decreased to provide the required capacitance betweenthe gate and the channel region. For example, a channel length ofapproximately 0.08 μm may require a gate dielectric made of silicondioxide as thin as approximately 1.2 nm. Although, generally, usage ofhigh speed transistor elements having an extremely short channel may berestricted to high speed applications, whereas transistor elements witha longer channel may be used for less critical applications, such asstorage transistor elements, the relatively high leakage current causedby direct tunneling of charge carriers through an ultra-thin silicondioxide gate insulation layer may reach values for an oxide thickness inthe range or 1-2 nm that may no longer be compatible with requirementsfor performance driven circuits.

Therefore, replacing silicon dioxide, or at least a part thereof, as thematerial for gate insulation layers has been considered, particularlyfor extremely thin silicon dioxide gate layers. Possible alternativedielectrics include materials that exhibit a significantly higherpermittivity so that a physically greater thickness of a correspondinglyformed gate insulation layer nevertheless provides a capacitive couplingthat would be obtained by an extremely thin silicon dioxide layer.Commonly, a thickness required for achieving a specified capacitivecoupling with silicon dioxide is referred to as capacitance equivalentthickness (CET). Thus, at a first glance, it appears that simplyreplacing the silicon dioxide with high-k materials is a straightforwardway to obtain a capacitance equivalent thickness in the range of 1 nmand less.

It has thus been suggested to replace silicon dioxide with highpermittivity materials, such as tantalum oxide (Ta₂O₅), with a k ofapproximately 25, strontium titanium oxide (SrTiO₃), having a k ofapproximately 150, hafnium oxide (HfO₂), HfSiO, zirconium oxide (ZrO₂)and the like.

When advancing to sophisticated gate architecture based on high-kdielectrics, additionally, transistor performance may also be increasedby providing an appropriate conductive material for the gate electrodeto replace the usually used polysilicon material, since polysilicon maysuffer from charge carrier depletion at the vicinity of the interface tothe gate dielectric, thereby reducing the effective capacitance betweenthe channel region and the gate electrode. Thus, a gate stack has beensuggested in which a high-k dielectric material provides enhancedcapacitance even at a less critical thickness compared to a silicondioxide layer, while additionally maintaining leakage currents at anacceptable level. On the other hand, metal-containing non-polysiliconmaterial, such as titanium nitride, aluminum oxide and the like, may beformed so as to directly connect to the high-k dielectric material,thereby substantially avoiding the presence of a depletion zone. Sincetypically a low threshold voltage of the transistor, which representsthe voltage at which a conductive channel forms in the channel region,is desired to obtain the high drive currents, commonly, thecontrollability of the respective channel requires sophisticated lateraldopant profiles and dopant gradients, at least in the vicinity of the PNjunctions. Therefore, so-called halo regions are usually formed by ionimplantation in order to introduce a dopant species whose conductivitytype corresponds to the conductivity type of the remaining channel andsemi-conductor region to “reinforce” the resulting PN junction dopantgradient after the formation of respective extension and deep drain andsource regions. In this way, the threshold voltage of the transistorsignificantly determines the controllability of the channel, wherein asignificant variance of the threshold voltage may be observed forreduced gate lengths. Hence, by providing an appropriate haloimplantation region, the controllability of the channel may be enhanced,thereby also reducing the variance of the threshold voltage, which isalso referred to as threshold roll-off, and also reducing significantvariations of transistor performance with a variation in gate length.Since the threshold voltage of the transistors is significantly affectedby the work function of the gate material that is in contact with thegate dielectric material, an appropriate adjustment of the effectivework function with respect to the conductivity type of the transistorunder consideration has to be guaranteed.

For example, appropriate metal-containing gate electrode materials, suchas titanium nitride, aluminum oxide and the like, may frequently beused, wherein the corresponding work function may be adjusted so as tobe appropriate for one type of transistor, such as N-channeltransistors, while P-channel transistors may require a different workfunction and thus a differently treated metal-containing electrodematerial in order to obtain the desired threshold voltage. In this case,complex and sophisticated manufacturing regimes may be required toprovide different gate electrode materials in order to comply with therequirements of different transistor types. For this reason, it has alsobeen proposed to appropriately adjust the threshold voltage oftransistor devices by providing a specifically designed semi-conductormaterial at the interface between the high-k dielectric material and thechannel region of the transistor device, in order to appropriately“adapt” the band gap of the specifically designed semiconductor materialto the work function of the metal-containing gate electrode material,thereby obtaining the desired low threshold voltage of the transistorunder consideration. Typically, a corresponding specifically designedsemiconductor material, such as silicon/germanium and the like, may beprovided by an epitaxial growth technique, which may also present anadditional complex process step, which, however, may provide reducedoverall process complexity compared to the provision of the differentmetal-containing gate electrode materials or which may provide increasedflexibility in obtaining appropriate transistor characteristics.

It turns out, however, that the manufacturing sequence for providing thethreshold adjusting semiconductor alloy may have a significant influenceon threshold variability across an active region, as will be explainedin more detail with reference to FIGS. 1 a-1 f.

FIG. 1 a schematically illustrates a cross-sectional view of asemiconductor device 100 comprising a substrate 101, above which isformed a silicon-containing semiconductor material 103 having anappropriate thickness for forming therein and thereabove transistorelements. In the example shown, a buried insulating layer 102, forinstance in the form of a silicon dioxide material, is positionedbetween the substrate 101 and the silicon-containing semiconductor layer103. Moreover, an isolation structure 104, such as a shallow trenchisolation, is formed in the semiconductor layer 103 to define a firstcrystalline “active” region 103A and a second active region 103B. Inthis context, an active region is to be understood as a semiconductormaterial in which an appropriate dopant profile is to be created inorder to form PN junctions for one or more transistor elements. In theexample shown, the first active region 103A may correspond to one ormore P-channel transistors while the second active region 103B maycorrespond to one or more N-channel transistors. Furthermore, in themanufacturing stage shown, a silicon dioxide mask layer 105 is formedabove the first and second active regions 103A, 103B, while typicallythe silicon dioxide material of the layer 105 may not be formed on theisolation structure 104, since typically the material of the layer 105may be formed as a thermal oxide material.

The semiconductor device 100 as illustrated in FIG. 1 a may typically beformed on the basis of the following process techniques. First, theisolation structure 104 is formed on the basis of well-establishedlithography, etch, deposition, planarization and anneal techniques inwhich, for instance, a trench is formed in the semiconductor layer 103on the basis of a lithography process, which is subsequently filled withan appropriate insulating material such as silicon dioxide, siliconnitride and the like. After removing any excess material, furtherprocessing is typically continued by performing implantation sequencesusing an appropriate mask regime in order to introduce the appropriatedopant species for the active regions 103A, 103B. It should beappreciated that, although sophisticated planarization techniques maytypically be used during the formation of the isolation structure 104,nevertheless a more or less pronounced surface topography may beobtained after the above-described process sequence so that the materialof the active regions 103A, 103B may extend above the surface 104S ofthe isolation structure 104. Thereafter, the silicon dioxide 105 may beformed, for instance, by oxidation on the basis of appropriatelyselected process parameters in order to obtain a desired thickness ofthe layer 105, which may act as a growth mask during the furtherprocessing of the semiconductor device 100. That is, as previouslydiscussed, the active region 103A has to be exposed prior to performinga selective epitaxial growth process for depositing a silicon/germaniumalloy that may provide the required band gap offset or threshold voltageadjustment for corresponding P-channel transistors to be formed in andabove the active region 103A.

FIG. 1 b schematically illustrates the semiconductor device in a furtheradvanced manufacturing stage in which a resist mask 106 is formed abovethe second active region 103B. The resist mask may be formed bylithography techniques in accordance with similar recipes as may also beused for the masking regime when introducing the corresponding welldopant species into the active regions 103A, 103B. Thus, afterpatterning the resist mask 106, the active region 103A is exposed to awet chemical etch ambient 107, which may be performed on the basis ofhydrofluoric acid (HF), which may efficiently remove silicon dioxideselectively to silicon material. Thus, the exposed portion of the masklayer 105 is effectively removed wherein, however, the previouslycreated surface topography with respect to the regions 103A, 103B andthe isolation structure 104 may typically be maintained or may be evenfurther increased. Next, a further wet chemical etch process istypically performed to remove the resist mask 106 on the basis ofwell-established etch recipes wherein, depending on the chemistry used,the resulting surface topography may further be increased.

FIG. 1 c schematically illustrates the semiconductor device 100 afterthe above-described process sequence and prior to actually depositingthe silicon/germanium alloy on the exposed active region 103A. Asillustrated, the moderately pronounced surface topography may result inthe exposure of a horizontal surface portion 103H and also of asubstantially vertical surface portion 103V, wherein both portions mayact as deposition surface areas during the subsequent epitaxial growthprocess.

FIG. 1 d schematically illustrates the semiconductor device 100 during aselective epitaxial growth process 108 in which process parameters areselected in accordance with well-established recipes such that asignificant material deposition may be restricted to the exposed surfaceareas 103H, 103V (FIG. 1 e), while a material deposition on dielectricsurface areas, such as the isolation structure 104 and the silicondioxide mask layer 105, may be negligible. Consequently, during theselective epitaxial growth process 108 a silicon/germanium alloy 109 maybe selectively formed on the active region 103A, wherein the surfaceportions 103H, 103V may act as a template material. For instance, insophisticated applications, the silicon/germanium alloy 109 may have tobe provided with a desired target thickness, for instance ofapproximately 10 nm, when a germanium concentration of approximately 25atomic percent is used. It should be appreciated that the materialcomposition of the silicon/germanium alloy 109 as well as the thicknessthereof may have a significant influence on the finally obtainedthreshold voltage and thus the finally obtained transistorcharacteristics. Although the material composition may be controlledwith a high degree of accuracy, a significant degree of thresholdvariability may be observed in completed semiconductor devices, which isbelieved to be caused by a thickness variation in the silicon/germaniumalloy. Without intending to restrict the present disclosure to anytheory, it is nevertheless assumed that a difference of growth rate mayoccur during the deposition process 108, which may have its origin inthe different crystallographic orientations of the exposed surface areas103H, 103V. That is, as illustrated in FIG. 1 d, the semiconductor layer103 may be provided as a crystalline material having a surfaceorientation (100) while a transistor length direction and widthdirections are typically aligned with respect to the crystallographic<110> direction. Consequently, in particular at the area in the vicinityof the isolation structure 104, in which the surface portion 103V mayhave a substantially (110) orientation and in the area of acorresponding rounded portion 103R (see FIG. 1 c), othercrystallographic directions may be present, thereby resulting in anincreased growth rate compared to central portions having substantiallythe (100) orientation. As a consequence, a thickness 109P at theperiphery of the active region 103A may be greater compared to athickness 109C in the center of the active region 103A, thereby possiblyresulting in a threshold variability across the active region 103A.

FIG. 1 e schematically illustrates the semiconductor device 100 in afurther advanced manufacturing stage. As illustrated, one or moreP-channel transistors 150A are formed in and above the active region103A on the basis of respective silicon/germanium alloys, which may bereferred to as alloys 109C, 109P, since these materials may have adifferent thickness, as previously explained with reference to FIG. 1 d.Furthermore, an N-channel transistor 150B is formed in and above theactive region 103B. The transistors 150A, 150B comprise an electrodestructure 151 including a gate insulation layer 151B, comprising ahigh-k dielectric material, as is previously explained. Furthermore, ametal-containing electrode material, such as aluminum oxide, titaniumnitride and the like, may be formed on the gate insulation layer 15113,followed by a further electrode material, such as polysilicon 151C. Asillustrated, in the P-channel transistors 150A, the gate insulationlayers 151B are formed on the corresponding silicon/germanium alloys109C, 109P, respectively, so that a threshold voltage of the transistors150A, i.e., the voltage at which a conductive channel forms in a channelregion 153, may be determined by the characteristics of the alloys 109C,109P and the materials 151B and 151A in combination with thecorresponding characteristics of drain and source regions 154, which mayalso be formed on the basis of sophisticated dopant profiles, aspreviously explained. On the other hand, the band gap configuration ofthe channel region 153 of the N-channel transistor 150B is appropriatefor the corresponding materials 151B, 151A of the transistor 150B. Thus,in this configuration, although the silicon/germanium alloy may beformed on the basis of a specifically selected target thickness, whichmay result in substantially the same threshold voltages for transistors150A, the previously occurring deposition non-uniformity may thuscontribute to a corresponding difference in transistor characteristics,even if the remaining manufacturing processes for forming the gateelectrode structure 151 and the drain and source regions 154 may beperformed with a high degree of process uniformity.

FIG. 1 f schematically illustrates a cross-sectional view in order todepict a P-channel transistor, such as one of the transistors 150A ofFIG. 1 e, along a transistor width direction. Thus, as illustrated, thegate electrode structure 151 may extend across the entire active region103A and may also be formed above a portion of the isolation structure104. Due to the deposition non-uniformities previously described, thesilicon/germanium alloy 109 may comprise the peripheral portion 109P andthe central portion 109C, which may thus differ in thickness, asdiscussed above. Consequently, also within a single transistor element,a pronounced thickness variation of the silicon/germanium alloy mayexist so that an overall threshold voltage may be obtained that may bedifficult to be predicted due to the varying thickness of thesilicon/germanium alloy 109. Moreover, for a difference in transistorwidth of various active regions, a further pronounced thresholdvariability may occur since, for an increased overall transistor width,the edge effect at the isolation structure 104 may be less pronouncedcompared to a transistor active region having a reduced width.Consequently, the dependence of the threshold voltage on the transistorwidth may be significantly increased due to the thickness variation ofthe silicon/germanium material, even within a single transistor element,thereby contributing to a significant overall device variability, whichmay not be compatible with performance requirements of sophisticatedsemiconductor devices.

The present disclosure is directed to various methods and devices thatmay avoid, or at least reduce, the effects of one or more of theproblems identified above.

SUMMARY OF THE INVENTION

The following presents a simplified summary of the invention in order toprovide a basic understanding of some aspects of the invention. Thissummary is not an exhaustive overview of the invention. It is notintended to identify key or critical elements of the invention or todelineate the scope of the invention. Its sole purpose is to presentsome concepts in a simplified form as a prelude to the more detaileddescription that is discussed later.

Generally, the present disclosure provides methods and semiconductordevices in which threshold variability may be reduced by enhancing thesurface topography of active semiconductor regions prior to performing aselective epitaxial growth process. To this end, material of the activeregion under consideration may be removed in a highly controllablemanner so as to significantly reduce the growth rate variability duringthe subsequent epitaxial growth process. For this purpose, in someillustrative embodiments, plasma assisted etch recipes may be used, forinstance in the context of patterning growth masks, thereby obtainingreduced pronounced surface topography, which may thus provide enhanceduniformity during the epitaxial growth process.

One illustrative method disclosed herein comprises forming a mask layeron a first silicon-containing crystalline semiconductor region and asecond silicon-containing crystalline semiconductor region, wherein thefirst and second silicon-containing semiconductor regions are laterallyseparated by an isolation region. The method further comprises removingthe mask layer selectively from the first silicon-containing crystallinesemiconductor region while maintaining the mask layer on the secondsilicon-containing crystalline semiconductor region. Furthermore, thefirst silicon-containing crystalline semiconductor region is recessedand a threshold adjusting semiconductor alloy is selectively formed onthe recessed first silicon-containing crystalline semiconductor region.The method further comprises forming a first gate electrode structure ofa first transistor above the threshold adjusting semiconductor alloy andforming a second gate electrode structure of a second transistor abovethe second silicon-containing crystalline semiconductor region.

A further illustrative method disclosed herein comprises exposing asurface of an active semiconductor region that is laterally enclosed byan isolation structure wherein any exposed surface areas of the exposedsurface have substantially the same crystalline orientation. Moreover,the method comprises forming a threshold adjusting semiconductormaterial on the exposed surface by performing a selective epitaxialgrowth process. Finally, the method comprises forming a gate electrodestructure of a transistor on the threshold adjusting semiconductormaterial wherein the gate electrode structure comprises a high-kdielectric material and a metal-containing electrode material formed onthe high-k dielectric material.

One illustrative semiconductor device disclosed herein comprises anactive silicon-containing semiconductor region and an isolationstructure laterally enclosing the active silicon-containingsemiconductor region, wherein the isolation structure has a first edgeand a second edge that define a width of the active silicon-containingsemiconductor region. The semiconductor device further comprises athreshold adjusting semiconductor alloy formed on the activesilicon-containing semiconductor region and extending from the firstedge to the second edge and having a thickness with a variation ofapproximately 5 percent or less. Moreover, the semiconductor devicecomprises a gate electrode structure comprising a high-k gate insulationlayer and a metal-containing electrode material that is formed on thehigh-k gate insulation layer.

BRIEF DESCRIPTION OF THE DRAWINGS

The disclosure may be understood by reference to the followingdescription taken in conjunction with the accompanying drawings, inwhich like reference numerals identify like elements, and in which:

FIGS. 1 a-1 d schematically illustrate cross-sectional views duringvarious manufacturing stages in selectively forming a silicon/germaniumalloy on an active region of a P-channel transistor, according toconventional strategies;

FIGS. 1 e-1 f schematically illustrate cross-sectional views oftransistor elements formed on the basis of the preceding conventional,process strategy, thereby obtaining a pronounced threshold voltagevariability, which is believed to be caused by a non-uniformity ofgrowth rates;

FIGS. 2 a-2 b schematically illustrate cross-sectional views of asemiconductor device during the deposition and patterning of a maskmaterial wherein the patterning may be accomplished on the basis of aplasma-assisted etch process, according to illustrative embodiments;

FIG. 2 c schematically illustrates the semiconductor device during themanufacturing phase in which a certain degree of material removal andthus recessing of the active region may be accomplished, therebyenhancing surface topography prior to selective epitaxial growthprocess, according to further illustrative embodiments;

FIGS. 2 d-2 e schematically illustrate cross-sectional views of thedevice during further manufacturing steps for forming a thresholdadjusting semiconductor alloy, according to illustrative embodiments;

FIG. 2 f schematically illustrates a top view of the semiconductordevice after the epitaxial growth of the threshold adjustingsemiconductor alloy; and

FIGS. 2 g-2 h schematically illustrate cross-sectional views of thesemiconductor device in a very advanced manufacturing stage in whichsophisticated gate electrode structures including a high-k gateinsulation material may be formed on the basis of the thresholdadjusting semiconductor alloy having a reduced degree of thicknessvariability, according to still further illustrative embodiments.

While the subject matter disclosed herein is susceptible to variousmodifications and alternative forms, specific embodiments thereof havebeen shown by way of example in the drawings and are herein described indetail. It should be understood, however, that the description herein ofspecific embodiments is not intended to limit the invention to theparticular forms disclosed, but on the contrary, the intention is tocover all modifications, equivalents, and alternatives falling withinthe spirit and scope of the invention as defined by the appended claims.

DETAILED DESCRIPTION

Various illustrative embodiments of the invention are described below.In the interest of clarity, not all features of an actual implementationare described in this specification. It will of course be appreciatedthat in the development of any such actual embodiment, numerousimplementation-specific decisions must be made to achieve thedevelopers' specific goals, such as compliance with system-related andbusiness-related constraints, which will vary from one implementation toanother. Moreover, it will be appreciated that such a development effortmight be complex and time-consuming, but would nevertheless be a routineundertaking for those of ordinary skill in the art having the benefit ofthis disclosure.

The present subject matter will now be described with reference to theattached figures. Various structures, systems and devices areschematically depicted in the drawings for purposes of explanation onlyand so as to not obscure the present disclosure with details that arewell known to those skilled in the art. Nevertheless, the attacheddrawings are included to describe and explain illustrative examples ofthe present disclosure. The words and phrases used herein should beunderstood and interpreted to have a meaning consistent with theunderstanding of those words and phrases by those skilled in therelevant art. No special definition of a term or phrase, i.e., adefinition that is different from the ordinary and customary meaning asunderstood by those skilled in the art, is intended to be implied byconsistent usage of the term or phrase herein. To the extent that a termor phrase is intended to have a special meaning, i.e., a meaning otherthan that understood by skilled artisans, such a special definition willbe expressly set forth in the specification in a definitional mannerthat directly and unequivocally provides the special definition for theterm or phrase.

Basically, the present disclosure provides semiconductor devices andtechniques in which sophisticated gate electrode structures may beformed in an early manufacturing stage on the basis of a high-kdielectric material and a metal-containing electrode material. Thethreshold voltage of one type of transistor may, therefore, be adjustedby providing an appropriate semiconductor material in the channel regionof the corresponding transistors, which may be accomplished bymanufacturing process techniques with enhanced uniformity, therebyreducing the threshold variability compared to conventional strategies,as previously described. For this purpose, the surface topography of theexposed active region may be enhanced in order to reduce the number ofdifferent crystallographic orientations, which may typically be presentat the edge of active regions when a more or less pronounced surfacetopography has been generated during the preceding manufacturingprocesses. That is, by removing material of the exposed active region ina highly controllable manner, that is, in some illustrative embodiments,on the basis of a plasma-assisted etch process, a certain degree ofrecessing may be accomplished, thereby also reducing the amount ofundesired surface areas, such as substantially vertical surface orsidewall portions at the periphery of the exposed active region.Consequently, the influence of undesired crystallographic orientationson the growth rate during the selective epitaxial growth process may bereduced, thereby reducing the difference in thickness between centralareas and peripheral areas of the epitaxially grown semiconductormaterial. It should be appreciated that the term “thickness variabilityor uniformity” as used herein may be defined on the basis of thicknessof the semiconductor alloy in the center of an active region underconsideration by determining a percentage of deviation from this“reference” thickness at the periphery of the active region. Forinstance, a thickness of 10 nm at the center of the active region and athickness of 12 nm at the periphery thereof may correspond to athickness variability of 20 percent.

In some illustrative embodiments disclosed herein, the highlycontrollable material removal in the active region may be accomplishedduring a plasma-assisted etch process for patterning a mask layer,thereby maintaining a high degree of process efficiency with respect tothe conventional strategy, as previously described. For example, siliconnitride may be used as an efficient mask material which may beefficiently etched on the basis plasma-assisted etch chemistries usingchlorine or fluorine-based recipes, as are well established in the art.In other illustrative embodiments, an additional material removal may beapplied, if desired, for instance on the basis of well controllable wetchemical etch processes and the like. Consequently, based on theprevious plasma-assisted etch process, any desired degree of recessingmay be applied without contributing to pronounced growthnon-uniformities, as is typically caused in conventional strategies.

With reference to FIGS. 2 a-2 j, further illustrative embodiments willnow be described in more detail, wherein reference may also be made toFIGS. 1 a-1 f, if required.

FIG. 2 a schematically illustrates a cross-sectional view of asemiconductor device 200 comprising a substrate 201 and asilicon-containing semiconductor region 203, which may be in asubstantially crystalline state. Furthermore, in some illustrativeembodiments, as is, for instance, shown in FIG. 2 a, at least a portionof the device 200 may be formed on the basis of an SOI architecture inwhich a buried insulating layer 202 is positioned between the substrate201 and the semiconductor layer 203. It should be appreciated, however,that the principles disclosed herein may also be readily applied to abulk configuration in which the buried insulating layer 202 may beomitted, at least in some device areas of the semiconductor device 200.Furthermore, an isolation structure 204, such as a shallow trenchisolation, may be provided in the semiconductor layer 203, therebydefining a first active region 203A and a second active region 203B. Aspreviously explained with reference to the device 100, the activeregions 203A, 203B may comprise a basic dopant profile for defining theconductivity type of corresponding transistors still to be formed in andabove the active regions 203A, 203B. In one illustrative embodiment, theactive region 203A may represent an N-doped region in order to form oneor more P-channel transistors therein. Similarly, the active region 203Bmay represent the active region of one or more N-channel transistors. Inthe following, a manufacturing sequence will be described in which athreshold adjusting semiconductor alloy may be selectively formed on theactive region 203A in order to provide a corresponding threshold voltagefor one or more transistors to be formed therein. It should beappreciated, however, that corresponding mechanisms for adjusting thethreshold voltage may also be applied to any transistor to be formed inand above the active region 203B or to both active regions 203A, 203B,depending on the overall device and process requirements. Furthermore,in the manufacturing stage shown, a mask layer 205 may be formed abovethe active regions 203A, 203B with an appropriate thickness, forinstance with a thickness in the range of approximately 10 nm or less.In one illustrative embodiment, the mask layer 205 may be comprised ofsilicon nitride which may be formed in a highly controllable manner onthe basis of well-established deposition recipes. In other illustrativeembodiments, the mask layer 205 may be comprised of other materials,which may be selectively removed with respect to material of the activeregion 203A and the isolation structure 204 by using a plasma-assistedetch recipe. For instance, silicon carbide, nitrogen-containing siliconcarbide and the like represent appropriate materials that may be usedfor forming the mask layer 205.

The semiconductor device 200 may be formed on the basis ofwell-established process techniques, as also previously described withreference to the device 100, when the active regions 203A, 203B and theisolation structure 204 are considered. As previously discussed, duringthe corresponding manufacturing sequence, a more or less pronouncedsurface topography may be generated. Thereafter, the mask layer 205 maybe formed on the basis of a deposition process 215, such as a thermallyactivated chemical vapor deposition (CVD) process, a plasma-assisteddeposition process and the like. It should be appreciated that aplurality of deposition recipes are well established in the art so as toform a material layer, such as silicon nitride, silicon carbide and thelike, with a desired thickness in the above-specified range with a highdegree of uniformity.

FIG. 2 b schematically illustrates the semiconductor device 200 in afurther advanced manufacturing stage. As illustrated, an etch mask 206,such as a resist mask, is formed in such a manner that the mask layer205 above the active region 203B may be covered, while the portion ofthe mask layer 205 formed above the active region 203A may be exposed toa plasma-assisted etch ambient 217. As previously explained, the etchmask 206 may be formed on the basis of well-established photolithographytechniques. Thereafter, the plasma-assisted ambient of the etch process217 may be established, for instance on the basis of appropriate etchrecipes and process parameters, wherein a plurality of chlorine andfluorine-based chemistries are available for silicon nitride, siliconcarbide and the like, in a selective manner with respect to theisolation structure 204 and the material of the active region 203A.Thus, during the etch process 217, material of the layer 205 may beincreasingly removed, wherein finally during the advance of the etchfront the active region 203A may be exposed and may also interact withthe etch ambient 217, however, at a significantly reduced degreecompared to the material of the mask layer 205. Consequently, due to theanisotropic nature of the etch process 217, a certain degree ofrecessing of the active region 203A may be accomplished withoutcontributing to a pronounced corner rounding, as may typically occur onthe basis of wet chemical etch recipes, as previously discussed.

FIG. 2 c schematically illustrates the semiconductor device 200 in afurther advanced stage. As illustrated, a certain degree of recessing orthickness reduction, indicated as 203R, may be created, therebyenhancing the overall surface topography, i.e., reducing the heightdifference between the surface 203S and the surface 204S of theisolation region 204. As explained with reference to FIG. 2 b, in someillustrative embodiments, the recess 203R may be accomplished on thebasis of the etch process 217 (FIG. 2 b), for instance by appropriatelyselecting an etch time of the process 217 wherein appropriate values maybe obtained on the basis of test runs and the like. In otherillustrative embodiments, an additional plasma-assisted etch process217A may be performed after substantially completely removing theexposed portion of the mask layer 205, when the etch behavior of thematerial of the active region 203A is considered inappropriate withrespect to the etch chemistry of the process 217 of FIG. 2 b. Also, inthese embodiments, the recess 203R may be obtained in a highlycontrollable manner, thereby reducing the height difference between theregion 203A and the isolation structure 204, thereby also providing areduced degree of variability with respect to crystallographicorientations at the periphery of the active region 203A, as previouslyexplained.

FIG. 2 d schematically illustrates the semiconductor device 200 whensubjected to an etch sequence 218, which may include appropriate etchsteps for removing contaminants, such as etch byproducts created duringthe preceding etch process or processes 217, 217A and which may alsoinclude etch steps for removing the etch mask 206 (FIG. 2 c). Forexample, the etch sequence 218 may be performed on the basis ofhydrofluoric acid (HF) for cleaning exposed surface areas, wherein priorto or after, if desired, a dedicated etch chemistry may be applied toremove the etch mask 206 (FIG. 2 c). In some illustrative embodiments,the etch sequence 218 may further comprise a specific etch step forincreasing the degree of recessing, as indicated by 203D, wherein adesired “anisotropic” etch behavior may be accomplished due to thepreceding plasma-assisted etch step(s). That is, further to thepreceding recessing of the material of the active region 203A, a furtheretch step, even when exhibiting basically an isotropic behavior, mayresult in a uniform material removal, even at the vicinity of theisolation structure 204. For example, well-controllable and veryselective etch recipes are available, for instance based on tetra methylammonium hydroxide (TMAH), which basically represents a chemical agentfor etching resist material which, however, may also be used for etchingsilicon material in higher concentrations at elevated temperature,wherein a high degree of selectivity with respect to silicon dioxide,silicon nitride and the like may also be achieved. Consequently, basedon the corresponding etch chemistry, the further recessing 203D, ifdesired, may be accomplished, for instance, such that a correspondingthickness of the semiconductor alloy still to be formed may becompensated for in view of enhancing overall process uniformity.

FIG. 2 e schematically illustrates the semiconductor device 200 whenexposed to a deposition ambient 208, which is appropriately designed toselectively deposit a threshold adjusting semiconductor alloy 209 on theactive region 203A. For instance, the semiconductor alloy 209 maycomprise a silicon/germanium alloy with an appropriate germaniumfraction, such as 20 atomic percent or higher, depending on the overalldevice requirements. As previously explained, the resulting band gapoffset obtained by the material 209 may depend on the materialcomposition and the thickness. Hence, for both parameters, appropriatetarget values may be selected in order to obtain the desired thresholdvoltage. Due to the enhanced surface topography, the variability ingrowth rate during the process 208 may be significantly reduced, therebyobtaining a thickness 209P at the periphery of the active region 203Athat may exhibit a significantly reduced degree of deviation from athickness 209C at the center. In this respect, the variability inthickness of the material 209 may be approximately 5 percent and less,for instance, in some illustrative embodiments, a thickness variabilityof approximately 3 percent and less may be accomplished, while, in othercases, the variability may be 2 percent and less. It should beappreciated that the thickness variability may be understood in theabove-defined sense. Consequently, for instance, for a target thicknessof 9 nm of a silicon/germanium alloy having a germanium fraction of 25atomic percent, the corresponding difference between the peripheralthickness 209P and the central thickness 209C may be less thanapproximately 0.45 nm, while, in other cases, an even further enhanceduniformity may be accomplished.

It should be appreciated that other semiconductor alloys may be used, ifrequired, by corresponding threshold adjusting mechanisms, wherein anysuch materials may also be provided with enhanced uniformity due to thereduction of corresponding edge effects during the deposition that maybe caused by the difference in growth rate of different crystallographicorientations, as previously explained.

FIG. 2 f schematically illustrates a top view of the semiconductordevice 200 after the deposition of the semiconductor alloy 209 and theremoval of the mask layer 205 (FIG. 2 e). As is evident from FIG. 2 f,due to the superior thickness uniformity of the semiconductor alloy 209,an enhanced uniformity may be accomplished along a length direction,indicated as L, and also along a width direction, indicated as W.Consequently, a corresponding threshold variability of transistorelements, which may be formed in and above the active region 203A, maybe reduced, while the thickness variability within a single transistorelement along the width direction may also be reduced.

FIG. 2 g schematically illustrates a cross-sectional view of thesemiconductor device 200 along the transistor length direction, which inFIG. 2 g corresponds to the horizontal direction. As illustrated, aplurality of transistors 250A, such as P-channel transistors, may beformed in and above the active region 203A, while one or moretransistors 250B may be formed in and above the active region 203B. Thetransistors 250A, 250B may have a similar configuration as previouslydescribed with reference to the device 100. That is, the transistors250A, 250B may comprise a gate electrode structure 251 including a gateinsulation layer 251B, a metal-containing electrode material 251Adirectly formed on the gate insulation layer 251B, followed by a furtherelectrode material 251C, such as a polysilicon material, metal silicideand the like. Moreover, in the transistors 250A, the gate insulationlayers 251B may be formed on the threshold adjusting semiconductor alloy209 so as to obtain a desired threshold voltage for a channel region253, which comprises the alloy 209 in the transistors 250A. Due to thesuperior thickness uniformity of the semiconductor alloy 209, thetransistors 250A may exhibit a very similar threshold voltage, therebycontributing to overall uniformity of the device 200 with respect toperformance and reliability.

With respect to any manufacturing techniques for forming the transistors250A, 250B, the appropriate manufacturing regime may be used. The gateelectrode structures 251 may be formed by depositing an appropriate gatedielectric, which may comprise conventional dielectrics in combinationwith high-k materials, followed by the deposition of themetal-containing electrode material 251A, for instance in the form ofaluminum oxide, titanium nitride and the like. Thereafter, any furtherappropriate material, such as polysilicon, may be deposited andsubsequently the layer structure may be patterned on the basis ofsophisticated lithography techniques. Thereafter, the dopant profilesfor drain and source regions 254 may be obtained on the basis ofsophisticated implantation techniques, for instance using a sidewallspacer structure 252. Thereafter, the device 200 may be annealed inorder to activate dopant and re-crystallize implantation-induced damage.

FIG. 2 h schematically illustrates the semiconductor device 200according to a cross-sectional view along a transistor width direction,which corresponds to the horizontal direction of FIG. 2 h. For example,the cross-section may be made through one of the transistors 250A when aplurality of transistors are formed in and above the active region 203A.In other cases, a single transistor may be formed in and above theactive region 203A and the cross-section may be made through the gateelectrode structure along the width direction. Thus, the transistor 250Amay comprise the threshold adjusting semiconductor alloy 209 on which isto be formed the gate insulation layer 251B, followed by themetal-containing electrode material 251A and the further gate material251C. Due to the significantly reduced difference in thickness of thesemiconductor alloy 209, i.e., the thickness values 209P, 209C may havereduced variability within the above-specified range, the overallthreshold voltage of the transistor 250A may be defined with enhancedaccuracy and predict-ability, while at the same time the dependency ofthreshold variability on transistor width for transistor devices ofdifferent width may be significantly reduced.

As a result, the present disclosure provides semiconductor devices andtechniques in which enhanced uniformity of the growth rate of aselective epitaxial growth process may be accomplished so that athreshold adjusting semiconductor alloy may be provided with asignificantly reduced thickness variability and reduced variability withrespect to material composition at an early manufacturing stage. Thus,sophisticated gate electrode structures comprising a high-k gatedielectric in combination with a metal-containing electrode material maybe formed prior to forming drain and source regions, thereby providing ahigh degree of compatibility with well-established CMOS techniques.

The particular embodiments disclosed above are illustrative only, as theinvention may be modified and practiced in different but equivalentmanners apparent to those skilled in the art having the benefit of theteachings herein. For example, the process steps set forth above may beperformed in a different order. Furthermore, no limitations are intendedto the details of construction or design herein shown, other than asdescribed in the claims below. It is therefore evident that theparticular embodiments disclosed above may be altered or modified andall such variations are considered within the scope and spirit of theinvention. Accordingly, the protection sought herein is as set forth inthe claims below.

1-20. (canceled)
 21. A semiconductor device, comprising: an activesilicon-containing semiconductor region; an isolation structurelaterally enclosing said active silicon-containing semiconductor region,said isolation structure having a first edge and a second edge, saidfirst and second edges defining a width of said activesilicon-containing semiconductor region; a threshold adjustingsemiconductor alloy formed on said active silicon-containingsemiconductor region, said threshold adjusting semiconductor alloyextending from said first edge to said second edge and having athickness with a variation of approximately 5 percent or less; and agate electrode structure comprising a high-k gate insulation layer and ametal-containing electrode material formed on said high-k gateinsulation layer.
 22. The semiconductor device of claim 21, wherein anaverage thickness of said threshold adjusting semiconductor alloy isapproximately 10 nm or less.
 23. The semiconductor device of claim 22,wherein said threshold adjusting semiconductor alloy comprises asilicon/germanium alloy with a germanium concentration of approximately20 atomic percent or more.
 24. The semiconductor device of claim 21,wherein the threshold adjusting semiconductor alloy has a thickness witha variation of approximately 3% or less.
 25. The semiconductor device ofclaim 24, wherein the threshold adjusting semiconductor alloy has athickness with a variation of approximately 2% or less.
 26. Asemiconductor device, comprising: an active silicon-containingsemiconductor region; an isolation structure laterally enclosing saidactive silicon-containing semiconductor region, said isolation structurehaving a first edge and a second edge, said first and second edgesdefining a width of said active silicon-containing semiconductor region;a threshold adjusting semiconductor alloy formed on said activesilicon-containing semiconductor region, said threshold adjustingsemiconductor alloy extending from said first edge to said second edgeand having a thickness with a variation of approximately 5 percent orless; and a plurality of transistors formed over the threshold adjustingsemiconductor alloy in the active silicon-containing semiconductorregion.
 27. The semiconductor device of claim 26, wherein an averagethickness of said threshold adjusting semiconductor alloy isapproximately 10 nm or less.
 28. The semiconductor device of claim 27,wherein said threshold adjusting semiconductor alloy comprises asilicon/germanium alloy with a germanium concentration of approximately20 atomic percent or more.
 29. The semiconductor device of claim 26,wherein the threshold adjusting semiconductor alloy has a thickness witha variation of approximately 3% or less.
 30. The semiconductor device ofclaim 29, wherein the threshold adjusting semiconductor alloy has athickness with a variation of approximately 2% or less.
 31. Thesemiconductor device of claim 26, wherein each of the plurality oftransistors comprises a gate electrode structure comprising a high-kgate insulation layer and a metal-containing electrode material formedon said high-k gate insulation layer.
 32. The semiconductor device ofclaim 26, wherein the plurality of transistors comprise a plurality ofP-channel transistors.